I. Field
The present disclosure relates generally to the field of multi-processor systems and, more specifically, to techniques for resource management in multi-processor systems having a primary processor and pipelined secondary processors.
II. Background
In complex computer systems common workload is often performed in parallel by a plurality of processors. A multi-processor system typically includes a primary processor administering a plurality of pipelined (i.e., connected in series) processors or co-processors, which are collectively referred to herein as secondary processors. In some applications, master-slave relationship may be formed between the primary processor and secondary processors. Such multi-processor systems may be used, for example, for processing of large amounts of video data or rendering graphics, among other computationally intensive applications.
In operation, instructions and, occasionally, data blocks are forwarded by the primary or a respective intermediate secondary processor downstream to the adjacent secondary processor, and acknowledgements confirming completion of particular tasks (i.e., task status data) are communicated by the secondary processors upstream to the primary processor. During execution of an application program, the primary processor assigns new tasks to the secondary processors or re-allocates computational and memory resources in the system upon receipt of acknowledgements that the preceding tasks have been completed.
However, repetitive re-transmission of the acknowledgements to the primary processor through a chain of pipelined secondary processors takes substantial time and constitutes a computational overhead, which adversely affects overall performance and efficiency of the multi-processor system. In particular, delays associated with sequential re-transmission of the acknowledgements limit command throughput and design flexibility of such systems. Despite the considerable efforts in the art devoted to increasing efficiency of resource management in the multi-processor systems having pipelined secondary processors, further improvements would be desirable.